library ieee;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.cpu_utils.all;
use STD.textio.all; 

entity memory is
	generic(
		dbus_size: integer:=32;
		abus_size: integer := 7;
		Tpd : Time := unit_delay
	);
	port(
		--d_bus_in: in std_logic_vector (dbus_size-1 downto 0);
		--d_bus_out: out std_logic_vector (dbus_size-1 downto 0);
		d_bus: inout std_logic_vector (dbus_size-1 downto 0);
		a_bus: in std_logic_vector (abus_size-1 downto 0);
		rd, wr : in bit;
		clock: in bit;
		initialize: in bit
		--cs : in bit--chip select
	);
end memory;



architecture memory_arh of memory is
	subtype mem_word is std_logic_vector (dbus_size-1 downto 0);
	type mem_array is array (0 to 2**abus_size-1) of mem_word;
	signal mem : mem_array; --signal?
begin
  
	process(clock,rd, a_bus)
	begin
		--if clock'event and clock = '1' then
			--if cs = '1' then
				if rd = '1' then 
					d_bus<= mem(to_integer(a_bus)) after Tpd;
				else
				  d_bus<= (d_bus'range => 'Z');
				end if;
			--end if;
	--	end if;
	end process;
	
	process(clock,wr, a_bus, d_bus)
	begin
		--if clock'event and clock = '1' then
			--if cs = '1' then
				if wr = '1' then
						mem(to_integer(a_bus)) <= d_bus after Tpd;
				end if;
			--end if;
		--end if;
	end process;
	


end memory_arh;